2.5 and 3D Integration is becoming a reality in device manufacturing. A critical process step is the thinning of the silicon wafer to reveal the metal filled Through Silicon Via (TSV). Grinding is used to remove the bulk of the silicon wafer. Currently a multistep sequence of processes that includes chemical mechanical planarization (CMP) and plasma etching has been used to complete the final thinning of the silicon. However, this conventional process has a number of disadvantages associated therewith including but not limited to the complexity of the process and the associated costs. As described hereinafter, the present invention is directed at overcoming these deficiencies associated with the conventional process by providing a simple, cost effective method to wet etch the remaining silicon to reveal the TSVs.
TSV wafers (substrates) are manufactured by creating vias (holes) in the top surface of a substrate. These vias extend part way through the thickness of the wafer. The holes are then filled in with a conductive material, with or without an insulating liner. The bottom side of the wafer, opposite of where the vias were created, is then put through a grind process where mechanical grinding reduces the thickness of the substrate, effectively reducing the distance from the bottom of the via to the bottom surface of the substrate. Complete grinding of the substrate to expose the conductor is undesired as this would result in ions from the conductive material being smeared across the substrate surface, thereby altering the electrical properties at the contaminated sites and reducing yield. Any number of manufacturing steps can be performed on the top side of the wafer prior to further processing of the bottom side depending on the application. For example, for a device wafer, the full device structure and metallurgical components can be added to the top surface of the wafer. For 2.5D interposer applications, the top side wiring/interconnects can be completed. The wafer with vias is then typically mounted using an adhesive layer on a carrier wafer with the top of the wafer toward the carrier wafer.
The grinding process leaves a layer of substrate material above the vias that can be thicker at the edge, uniform across the wafer or thicker at the center of the wafer than at the edge (within wafer thickness variation). Likewise there can be a difference in height of the substrate material above the vias on a wafer to wafer basis (wafer to wafer thickness variation). These differences in the layer above the vias can be greater than the allowable difference in height of the exposed vias.
The carrier wafer and via wafer are mounted using an adhesive material. This adhesive layer can vary in thickness and uniformity, rendering exterior measurements ineffective at determining the thickness and uniformity of the material remaining in the top silicon wafer, above the end of the via.
Integrated circuit wafers, which typically are in the form of flat round disks (although other shapes are possible) and often are made from silicon, Gallium Arsenide, or other materials, may be processed using various chemicals. One process is the use of liquid chemical etchant to remove material from or on the substrate, this process is often referred to as wet etching. Commonly used methods include submerging the wafers in chemical baths (referred to as “batch processing” or “immersion processing”), or dispensing fluid on a wafer while spinning (referred to as “single wafer processing”). As wafer sizes increase and geometry sizes decrease, substantial benefits can be realized by employing single wafer processing inasmuch as the processing environment may be better controlled.
The etch rate of wet etch process will vary with changes in etchant concentration. The addition of small amounts fresh chemical etchant to sustain the etch rate is a common practice when the chemical etchant is recirculated. Typically the addition is based on a mathematical model based on wafers processed or elapsed time from etchant preparation. If there is no measurement feedback the etch rate will hold only as well as the mathematical model can predict the need to inject fresh chemical etchant. Likewise any external influences will not be accounted for and the etch rate will not remain constant. The depth of the etch process is a function of etch rate and time. Time is well controlled but the etch rate can vary based on several factors. Likewise the required depth to etch will vary as wafer to wafer there will be thickness variation. Accordingly the lack of a method to determine when the vias are exposed limits the capability to expose a precise depth on each wafer processed.
KOH (Potassium Hydroxide) is one etchant typically used because of its property to etch silicon selectively to conductors (such as Copper) and insulators (such as silicon oxide). After the KOH etch there remains residual Potassium on the surface of the wafer. The residual Potassium based particles and ions from the etch process will result in a change of electrical properties of the substrate surface that will result in yield loss if not removed after the etch process.
Similar to thinning TSV wafers, the conventional process for thinning non TSV wafers involves grinding to remove the bulk of the wafer and a multistep sequence of processes that includes chemical mechanical planarization (CMP) and plasma etching to complete the final thinning of the wafer. However, this conventional process has a number of disadvantages associated therewith including but not limited to the complexity of the process and the associated costs. As described hereinafter, the present invention is directed at overcoming these deficiencies associated with the conventional process by providing a simple, cost effective method to wet etch the remaining substrate to a desired thickness and surface uniformity.
Thus, there exists a need for a system and method for: (1) determining quantity and pattern of material to be removed from the substrate; (2) removing the material to the desired uniformity; (3) determining when to terminate the etch process in order to have exposed the vias to the desired depth and (4) cleaning up residual potassium from the TSV wafer surface without disturbing the exposed vias. The present invention achieves these objectives as described below.